The present invention relates to a data processing apparatus, its processing method, program product and mobile telephone apparatus. In particular, the present invention relates to a receiving side data processing apparatus in a HARQ (Hybrid Automatic Repeat Request) processing apparatus used in W-CDMA (Wideband-Code Division Multiple Access), its processing method, program product and mobile telephone apparatus.
The international standard association 3GPP (3rd Generation Partnership Project) for the third generation mobile radio communication system attempts to add a new function called HSDPA (High Speed Downlink Packet Access) to the W-CDMA standards in order to implement faster radio communication. One kind of characteristic processing that makes fast communication according to the HSDPA possible is HARQ (see 3GPP TS25.212 V5.6.0 (2003.9) 4.2.7, 4.5.4).
The HARQ is processing for conducting data retransmission efficiently when data cannot be received correctly at the receiving side. In the HARQ processing at the transmitting side, transmission data is divided into a plurality of groups. In the 3GPP, the groups are called processes. And retransmission in the HARQ is managed every process. As a result, it becomes possible to transmit and receive data of other processes while data retransmission of a certain process is being conducted.
FIG. 1 is a configuration diagram showing an example of a conventional transmitting side HARQ processing apparatus. FIG. 2 is a configuration diagram showing an example of a conventional receiving side HARQ processing apparatus.
With reference to FIG. 1, the conventional transmitting side HARQ processing apparatus 100 includes J (where J is a positive integer) rate matching units 101. Data 102 including N (where N is a positive integer and N>J) processes is supplied to the conventional transmitting side HARQ processing apparatus 100 as its input data. Its output data is interleaved by an interleave unit 103 and then output as output data 104 including N processes. The rate matching unit 101 conducts processing every J processes simultaneously, and consequently outputs N process data.
With reference to FIG. 2, a conventional receiving side HARQ processing apparatus 110 includes J HARQ synthesis units 111, a buffer 112, and K (where K is a positive integer and K<N) rate matching units 113. The output data 104 of the transmitting side HARQ processing apparatus 100 is supplied as an input. The input data 104 is deinterleaved in a deinterleave unit 114, and input to the receiving side HARQ processing apparatus 110.
HARQ processing in the receiving side HARQ processing apparatus 110 includes elementary processing called HARQ synthesis in the HARQ synthesis unit 111 and rate dematching in the rate dematching unit 113.
The HARQ synthesis is processing of adding data of a process that could not be received correctly and the same data that is retransmitted. As a result, the possibility that data can be received correctly at the time of retransmission is increased. The rate dematching is inverse processing to processing of adjusting difference in rate between transmission data and a physical channel, which is called rate matching.
If in the rate matching conducted in the transmitting side HARQ processing apparatus 100 the rate of the transmission data is higher than the rate of the physical channel, the rate of the transmission data is squared with the rate of the physical channel are by thinning (hereafter called “puncture”) some data in a transmission data train.
Conversely, if the rate of the transmission data is lower than the rate of the physical channel, the rate of the transmission data is squared with the rate of the physical channel by repeating (hereafter called “repeat”) some data in the transmission data train.
On the other hand, in the rate dematching, dummy data are inserted in locations of data thinned on the transmitting side, or data repeated on the transmitting side are deleted.
When implementing such HARQ processing conducted on the receiving side as an apparatus, the buffer 112 becomes necessary to store data transmitted last time until the same data is retransmitted, besides the HARQ synthesis unit 111 and the rate matching unit 113 as shown in FIG. 2. When implementing the buffer 112 by using a single-port memory, schemes described below are generally considerable. However, those schemes have problems.
Furthermore, an example of such techniques is disclosed in Japanese Patent Publication (JP-A) No. 2000-173261 (claim 1, paragraph 0005, and FIG. 1). During a first cycle, an address of each even-numbered value is supplied to a write port and an address of each odd-numbered value is supplied to a read port. During a subsequent second cycle, an address of each odd-numbered value is supplied to a write port and an address of each even-numbered value is supplied to a read port. Such a technique of switching the write port and the read port alternately in each cycle and conducting data writing and reading is disclosed.
Scheme 1: It is a scheme of implementing the buffer 112 by using one physical memory (buffer 112). If, for example, there are four processes (process 1, process 2, process 3 and process 4), data of these processes are disposed on one physical memory (buffer 112). FIG. 3 is a diagram showing the scheme 1. If it is attempted to execute the rate dematching on data of the process 2 and the HARQ synthesis on data of the process 3 simultaneously as shown in FIG. 3, accesses to the buffer 112 occur simultaneously and consequently access contention occurs. Therefore, the rate dematching and the HARQ synthesis cannot be executed simultaneously. The HARQ synthesis is executed after execution of the rate dematching is completed, or the rate dematching is executed after execution of the HARQ synthesis is completed. In this way, this scheme has a problem of lengthened execution time of the HARQ.
Scheme 2: FIG. 4 is a diagram showing a scheme 2. In the scheme 2, a buffer 112 is formed of a plurality of physical memories (RAMs 121 to 124), and physical memories and processes are assigned in one-to-one correspondence as shown in FIG. 4. In the example shown in FIG. 4, data of a process 1 is stored in the RAM 121, and data of a process 2 is stored in the RAM 122. Data of a process 3 is stored in the RAM 123, and data of a process 4 is stored in the RAM 124.
In this case, in the rate dematching conducted on the data of the process 2 and the HARQ synthesis conducted on the data of the process 3, accesses to the buffer 112 become accesses to different physical memories. In other words, the RAM 122 is accessed in the processing of the rate dematching and the RAM 123 is accessed in the processing of the HARQ synthesis. Therefore, simultaneous execution of the rate dematching and the HARQ synthesis becomes possible.
By the way, the data sizes of respective processes and the number of processes change dynamically during communication, according to the HSDPA standards. Therefore, it is necessary to dynamically change memory assignment of respective processes. FIG. 5 is a diagram showing access contention in the scheme 2. As shown in FIG. 5, there is a possibility of disposing data of two processes (the process 2 and the process 3 in an example shown in FIG. 5) on the same physical memory (RAM 122). In this case, access contention occurs and consequently the same problem as that in the scheme 1 occurs.
The above-described schemes of two kinds cannot eliminate the problem that the HARQ synthesis and the rate dematching cannot be executed simultaneously and consequently the execution time of the whole HARQ is long.
On the other hand, while the technique described in JP-A-2000-173261 is intended for access control on one dual port memory (a memory having one input port and one output port), the present invention is intended for two or more single port memories (memories each having one port that serves as both input port and output port), and its control method is entirely different from the technique described in JP-A-2000-173261.